1. Field of the Invention
The present invention relates to a technique for reducing an error generated in the duty ratio of an output signal with respect to the duty ratio of an input signal in a level shift device which outputs the input signal after shifting the level of the signal by a prescribed amount.
2. Description of the Related Art
FIG. 4 shows a structure of a conventional level shift device which outputs an input signal after shifting the level of the signal by a prescribed amount. This level shift device comprises a complementary signal generating circuit 10 having a low-potential power source VDD1 as a voltage source, and a level shift circuit 20 having a high-potential power source VDD2 as a voltage source. The level shift device shifts the level of input signal Sin of the low-potential power source VDD1 to the output signal of the high-potential power source VDD2. Reference numerals In1-In4 are inverters of the complementary signal generating circuit 10, QP1-QP4 are PMOS transistors of the level shift circuit 20, QN1-QN4 are NMOS transistors, LH is an R-S latch circuit, and In5, In6, and In8 are inverters.
The action of the level shift device shown in FIG. 4 will be described by referring to a timing chart shown in FIG. 5. The input signal Sin that is inputted to the level shift device is shown in (a) of FIG. 5. The input signal Sin is supplied first to the inverters In2 and In3 via the inverter In1. Further, the input signal Sin is supplied to the inverter In4 via the inverter In3. At that time, output signal S1 of the inverter In2 becomes a normal signal that has a delay τ1 with respect to the input signal as shown in (b) of FIG. 5. Meanwhile, output signal S2 of the inverter In4 becomes an inverted signal that has a delay τ2 with respect to the input signal as shown in (c) of FIG. 5.
The output signal S1 of the inverter In2 is supplied to the gate of the NMOS transistor QN2 of the level shift circuit 20. As shown in (b) of FIG. 5, when a high-level signal is supplied to the gate of the NMOS transistor QN2 at time T2, the NMOS transistor QN2 turns to an ON state. At that time, a feedback signal (inverted signal of a signal S5) from the inverter In5 is high-level, so that the NMOS transistor QN1 turns to an ON state, and the PMOS transistor QP1 turns to an OFF state. Further, since its gate is earthed, the PMOS transistor QP2 is always in an ON state. The on-resistance of the PMOS transistor QP2 is set as a higher resistance than those of the NMOS transistors QN2 and QN1. With this, when a high-level signal is supplied to the gate of the NMOS transistor QN2 at the time T2, input signal S3 to a NAND circuit N1 of the R-S latch circuit LH becomes low-level as shown in (d) of FIG. 5. Thus, the output signal S5 of the NAND circuit N1 gradually becomes high-level from the time T2 onward of (f) in FIG. 5 due to the gate capacity of the inverter In5. The output signal S5 is supplied to the inverter In5. Further, after its polarity is inverted, the output signal S5 is supplied to the gates of the PMOS transistor QP1 and the NMOS transistor QN1.
Through this, the fall edge of input signal S3 inputted to the NAND circuit N1 of the R-S latch circuit LH is fed back as the fall edge of the input to the gates of the PMOS transistor QP1 and the NMOS transistor QN1 after a delay of a prescribed amount of time. Due to the feedback signal, the PMOS transistor QP1 turns to an ON state, the NMOS transistor QN1 turns to an OFF state, and the input signal S3 to the NAND circuit N1 of the R-S latch circuit LH becomes high-level.
At that time, the other input signal S6 of the NAND circuit N1 is low-level, so that the output signal S5 of the NAND circuit N1 is maintained as high-level.
In the meantime, output signal S2 of the inverter In4 is supplied to the gate of the NMOS transistor QN4 of the level shift circuit 20. As shown in (c) of FIG. 5, when a high-level signal is supplied to the gate of the NMOS transistor QN4 at time T12, the NMOS transistor QN4 turns to an ON state. At that time, a feedback signal (inverted signal of a signal S6) from the inverter In6 is high-level, so that the NMOS transistor QN3 turns to an ON state, and the PMOS transistor QP4 turns to an OFF state. Further, since its gate is earthed, the PMOS transistor QP3 is always in an ON state. The on-resistance of the PMOS transistor QP3 is set as a higher resistance than those of the NMOS transistors QN4 and QN3. With this, when a high-level signal is supplied to the gate of the NMOS transistor QN4 at time T12, input signal S4 to a NAND circuit N2 of the R-S latch circuit LH becomes low-level as shown in (e) of FIG. 5. Thus, the output signal S6 of the NAND circuit N2 gradually becomes high-level from the time T12 onward in (g) of FIG. 5 due to the gate capacity of the inverter In6. The output signal S6 is supplied to the inverter In6. Further, after its polarity is inverted, the output signal S6 is supplied to the gates of the PMOS transistor QP4 and the NMOS transistor QN3.
That is, the fall edge of the input signal S4 inputted to the NAND circuit N2 of the R-S latch circuit LH is fed back as the fall edge of the input to the gates of the PMOS transistor QP4 and the NMOS transistor QN3 after a delay of a prescribed amount of time. Due to the feedback signal, the PMOS transistor QP4 turns to an ON state, the NMOS transistor QN3 turns to an OFF state, and the input signal S4 to the NAND circuit N2 of the R-S latch circuit LH becomes high-level. At that time, the other output signal S5 of the NAND circuit N2 is low-level, so that the output signal S6 of the NAND circuit N2 is maintained as high-level.
Therefore, when a high-level signal is supplied to the gates of the NMOS transistors QN2, QN4, the output signals S5, S6 of the NAND circuits N1, N2 turn to high-level after a delay of a prescribed amount. The NAND circuits N1 and N2 are in feedback connection where the output of each NAND circuit is fed back to the input of the other. Thus, when the output signal S5 of the NAND circuit N1 becomes high-level at time T3, the output signal S6 of the NAND circuit N2 turns to low-level gradually due to the gate capacity of the inverter In6 as shown in (g) of FIG. 5. Further, when the output signal S6 of the NAND circuit N2 becomes high-level at time T13, the output signal S5 of the NAND circuit N1 turns to low-level gradually due to the gate capacity of the inverter In5 as shown in (h) of FIG. 5.
The output signal S6 of the NAND circuit N2 is outputted after the polarity thereof being inverted by an inverter In8. Thus, level-shift output signal S8 that is the output of the inverter In8 becomes the one as shown in (h) of FIG. 5. The rise edge of the level-shift output signal S8 has a delay τP with respect to the fall edge of the input signal S3 of the NAND circuit N1 shown in (d) of FIG. 5. Meanwhile, the fall edge of the level-shift output signal S8 has a delay τR with respect to the fall edge of the input signal S4 of the NAND circuit N2 shown in (e) of FIG. 5.
Now, high-level period TH and low-level period TL of the level-shift output signal S8 will be investigated. Assuming that the duty ratio of the input signal Sin to the complementary signal generating circuit 10 is 50%, and the half wavelength is T0, the high-level period TH can be expressed asTH=T0−(τ1+τP)+(τ2+τR), and the low-level period TL can be expressed asTL=2×T0−TH.
Therefore, provided that TL>TH, the difference ΔT between the high-level period TH and the low-level period TL can be expressed asΔT=TL−TH=2{(τ1−τ2)+(τP−τR)}.
Assuming that τ2=2×τ1, and τP=2×τR, for example, it can be expressed asΔT=2(τR−τ1).
When the above is looked at on the basis of the output signal S2 of the inverter In4 from a different point of view, the fall edge (at time T13) of the level-shift output signal SB has a delay τR with respect to the rise edge (at time T12) of the output signal S2. The output signal S1 of the inverter In2 is retarded with respect to the input signal Sin by the amount of time τ1 that is generated by the inverter In2. The output signal S2 of the inverter In4 is retarded with respect to the input signals Sin by the amount of time τ1′ that is generated the inverters In3 and In4. It is considered that τ1′=τ1, assuming that the inverters In2, In3, and In4 have the same characteristics.
The rise edge (at time T4) of the level-shift output signal S8 is retarded from the rise edge (at time T2′) of the output signal S2 by the amount ofτP−τ1′=τP−τ1=2τR−τ1.
That is, the delay of the rise edge of the level-shift output signal S8 with respect to the output signal S2 is (2τR−τ1), while the delay of the fall edge of the level-shift output signal S8 with respect to the output signal S2 is τR as mentioned above. Therefore, the high-level period TH of the level-shift output signal S8 is the length that is obtained by shortening the half wavelength T0 of the input signal Sin by the amount of (2τR−τ1)−τR=τR−τ1. In the meantime, the low-level period TL of the level-shift output signal S8 is the length that is obtained by extending the half wavelength T0 of the input signal Sin by the amount of (τR−τ1). Thus, the difference ΔT between the high-level period TH and the low-level period TL becomes asΔT=(τR−τ1)×2=2(τR−τ1), which is consistent with the explanation provided above.
Since τR≠τ1, the difference ΔT between the high-level period TH and the low-level period TL does not take a value, 0. That is, there is an error generated in the duty ratio of the level-shift output signal S8 with respect to the duty ratio of the input signal Sin.
As described, with the conventional circuit, there is a fluctuation generated between the duty ratios of both signals, due to a delay difference between the two signals generated in the complementary signal generating circuit and a delay in propagation of the signals of the R-S latch circuit used in the level shift circuit.